1. Technical Field
The present invention relates to a via arrangement structure of a semiconductor device having a multi-layered wiring layer.
2. Background Art
In recent years, for high speed performance of a semiconductor device such as an LSI (Large Scale Integrated circuit), an interlayer insulation film having a low dielectric constant (Low-k), which forms a multilayer wiring of the semiconductor device, has been actively developed. In general, the film having the low dielectric constant is formed by decreasing the density of a material used in the film or by removing the polarity of the material used in the film. However, in the film formed in this way, physical properties such as Young's modulus are generally deteriorated, and thus, the mechanical strength is decreased.
Further, conventionally, a CMP (Chemical-Mechanical Polishing) process has been widely used in the formation of a wiring layer. In the CMP process, in order to secure flatness of the wiring layer, a wiring which electrically functions as a circuit and a dummy wiring which does not electrically function as the circuit are formed. The dummy wiring functions not only to secure the flatness, but also to secure the mechanical strength of the interlayer insulation film according to the recent interlayer insulation film having lowered k.
Further, in a case where the Low-k material is also used in a via layer between upper and lower wiring layers, the mechanical strength of the via layer also causes a problem. That is, the mechanical strength of the multilayer wiring in the stacking direction (longitudinal direction) is decreased, which may damage reliability of the wiring. Thus, a dummy via which does not electrically function as a circuit is also provided in the via layer between the upper and lower wiring layers. The dummy via is not connected to the wiring which forms the circuit, but is connected to the dummy wiring. Further, in general, a dummy via design standard which is regulated by a design standard or the like determined for each semiconductor process is regulated by the density per unit area, the presence or absence of a dummy wiring positioned in the upper and lower layers of the dummy via, the overhang amount with respect to the dummy wiring, and the like, in a similar way to the dummy wiring.
In this regard, in general, the density of the sum of dummy vias and vias is not as high as the density (for example, 20% to 80%) of the sum of the dummy wiring and the wiring. Further, a design standard relating to the density of the sum of the dummy vias and the vias provides a relatively small value with only a restriction of a lower limit value which is greater than 0.1%, for example. In general, in order to comply with the design standard, the dummy via is disposed in an overlap region between two layers of the upper and lower wiring layers.
Further, in general, the shape of the dummy wiring is a shape in which a line and a space are repeated, in a similar way to the wiring. Further, in a case where the extension directions of two layers of the respective upper and lower dummy wirings are orthogonal to each other, the dummy vias are arranged with a uniform pitch in a matrix direction within a range where a design standard relating to an interval between vias or the like is complied with, in an overlap region formed by intersection of the dummy wirings orthogonal to each other in the upper and lower layers.
PTL1 discloses an example of a technique in which dummy contacts are provided to suppress the loading effect. Further, PTL2 discloses an example of a technique in which dummy vias or dummy contacts are arranged to reduce via defects or contact defects.